The present invention relates to a packet transfer control apparatus, and more particularly, to a packet transfer control apparatus which employs a direct memory access (DMA) transfer.
In order to rapidly transfer quantities of data, an interface unit as a transfer controller according to the IEEE 1394 standard is employed. The interface unit is controlled by a microprocessor unit (MPU). In the packet transfer technique defined in the IEEE 1394 standard, a packet including data and header information is transferred. The MPU receives the packet and decodes the header information included in the packet to determine how the data that follows the header information is to be processed. The IEEE protocol defines the amount of data which can be stored in one packet. Using this transfer technique, data having an increased amount of information, such as image information, cannot be stored in one packet. Therefore, the data must be divided into a plurality of blocks. Thus, a packet including header information is formed for each data block, and a plurality of packets are transferred in succession to achieve a transfer of a large quantity of data. The MPU receives and stores the divided data in a memory in sequential order so that it can recover the original data. Such packets are often used in the display of a picture such as a moving picture and thus are transmitted in succession in a short time, increasing the load on the MPU.
A direct memory access (DMA) transfer technique transfers quantities of data and allows data from an external unit to be downloaded into the memory without using the MPU.
Specifically, referring to FIG. 1, a packet transfer control apparatus (or node) 30 employing the DMA transfer technique comprises an interface 31, a buffer 32, an MPU 33, a DMA controller 34 and a memory 35. The interface 31 receives a packet including a header and data from a network, provides the header which is extracted from the packet to the MPU 33, and provides the data to the buffer 32. When the MPU 33 determines on the basis of header information that the received data is for the DMA transfer, the MPU 33 provides an enable signal to the DMA controller 34, which then initiates a data transfer between the buffer 32 and the memory 35.
The buffer 32 receives the DMA transfer data, transferred in succession, from the network. The DMA transfer data is then stored in the memory 35 under the control of the DMA controller 34. Thus, once the MPU 33 detects the DMA transfer addressed to its own node, the transfer between the buffer 32 and the memory 35 is controlled by the DMA controller 34, thus freeing the MPU 33 from the control of the data transfer.
Since the load on the MPU 33 is reduced by the use of the DMA transfer technique, the MPU 33 can perform other operations, such as data processing operations. In other words, the data input/output control between the buffer 32 and the memory 35 is occupied by the DMA controller 34 alone, and during such an interval, the MPU 33 is inhibited from performing such data transfer control.
Since interfacing by the MPU 33 is inhibited during the DMA transfer, the MPU 33 cannot accept a packet for an access demand from a node 41 when a node 40 is transferring packets to the node 30, as shown in FIG. 2. Accordingly, the node 30 cannot reply to the access demand. In this case, the node 41 retries the access demand until it receives a reply from the node 30. Thus, in the above described transfer technique, the operational efficiency of the remaining units connected to the network is lowered.
The lowering of the operational efficiency of the node 41 can be prevented if an xe2x80x9caccess rejectedxe2x80x9d reply is issued in response to the access demand, and the node 41 aborts the access demand and performs different operations. However, since no reply to the access demand is returned, the node 41 temporarily suspends operations. Alternatively, the node 41 only can perform a restricted operation.
It is an object of the invention to provide a packet transfer control apparatus which allows a processor to perform operations while a DMA operation is being performed.
In one aspect of the present invention, a packet transfer control apparatus for transferring a packet in the form of one of consecutive packets including blocks of data and a non-consecutive packet is provided. The apparatus includes a first buffer circuit for storing blocks of data included in the consecutive transfer packets. A memory unit is connected to the first buffer circuit and stores the blocks of data provided from the first buffer circuit. A direct memory access control unit is connected to the first buffer circuit and the memory unit and controls a direct transfer of the blocks of data between the first buffer circuit and the memory unit. A packet identification unit receives the packet and determining whether the packet is one of the consecutive packets and the non-consecutive packet and provides the consecutive packets to the first buffer circuit. A transmitting unit generates and transmits a response packet corresponding to the non-consecutive packet. The transmitting unit generates and transmits the response packet while the first buffer circuit and the memory unit perform the direct transfer operation.
In another aspect of the present invention, a method of transferring a packet in the form of a first packet including direct memory access data and a second packet including command data is provided. First, the first and second packets are received. Then, the direct memory access data included in the first packet is stored in a buffer circuit. The direct memory access data stored in the buffer circuit is transferred to a memory unit. The command data included in the second packet is processed simultaneously with the transfer step.
In yet another aspect of the present invention, a packet transfer apparatus connected to a bus is provided. The apparatus includes a receiving circuit connected to the bus for receiving a packet from the bus, the received packet including a header and data. A header identification circuit detects the received packet header and determining if the packet header indicates a DMA transfer. A first buffer stores the packet data when the packet header indicates a DMA transfer, as determined by the header identification circuit. A second buffer stores the packet data when the packet header does not indicate a DMA transfer, as determined by the header identification circuit. A memory stores the packet data received from the first buffer and for transferring stored data to the first buffer. A DMA controller controls a DMA operation between the first buffer and the memory and generates an interrupt signal indicating the DMA operation has been completed. A processor controls and performs non-DMA operations. A first transmit circuit forms and places a first transmit packet on the bus. When a DMA operation is being carried out by the memory and the first buffer, the processor is able to respond to a request from an external device using the first transmit circuit.